ASIC IP Digital Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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THE ROLE: 

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As an ASIC IP Digital Design Verification Engineer, you'll be a key contributor and part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. 

THE PERSON: 

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a great team player who has excellent written and verbal communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills with a willingness to learn new skills and ready to take on problems. Attention to detail is another critical skill for this position along with the ability to solve problems independently.

KEY RESPONSIBILITIES: 

• Design Verification of digital design blocks:
  • Study both high-level and micro architecture specifications and use Computer Architecture knowledge and background to gain an in depth understanding of new features or changes proposed in new projects.
  • Create test plans that outlines required verification work for project.
  • Produce verification code that tests RTL design functionality using UVM as per test plan.
  • Write cover points to make sure verification items are properly exercised.
  • Work on necessary debugging of verification code; fix tests to hit cover points if coverage is failing.
  • Learn & use Formal Verification techniques as needed
• Manage and monitor regressions (regular repeated runs of same set of mostly random tests) for team’s blocks and fix errors in failing tests.
• Generate and analyze coverage reports to ensure exhaustive verification of the design and all possible end-cases.
• Write and edit csh, perl, python or ruby scripts to automate verification as needed.
• Regular review and sign-off of design verification work at key project milestones.
• Collaborate with other senior DV engineers in the team, Program Managers and mentor juniors, interns and new-hires

PREFERRED REQUIREMENTS:

• Solid fundamental understanding of Computer Architecture and Digital Design concepts.
• Strong background in OOP coding techniques.
• Familiarity with scripting languages: perl or tcl or ruby or Bash or python, etc.
• Preferred to have prior experience with Verilog or SystemVerilog and UVM

ACADEMIC CREDENTIALS: 

• Undergrad degree required. Bachelors or Masters degree in Computer or Electrical Engineering, Computer Science, Engineering Science or similar preferred

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.